1. Field of the Invention
The present invention relates to apparatus and processes for packaging microelectronic dice. In particular, the present invention relates to a chip-on-flex packaging technology which includes at least one moisture barrier layer to prevent metal corrosion and delamination of flex component layers.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a "chip scale packaging" or "CSP".
One packaging technology, which is applicable to single chip packages and meets chip scale packaging goals, is called Chip-on-Flex ("COF") packaging. FIGS. 5a-5g illustrate an exemplary process for forming a COF package. As shown in FIG. 5a, a flex component 202 is attached (such as with a layer of adhesive--not shown) to an active surface 204 of a microelectronic die 206. The microelectronic die active surface 204 includes at least one contact 208. The microelectronic die 206 is then encapsulated with an encapsulating material 212, such as plastics, resins, and the like, as shown in FIG. 5b, that covers a back surface 214 and side(s) 216 of the microelectronic die 206, and abuts a bottom surface 218 of the flex component 202 (the portion not covered by the microelectronic die 206). The encapsulation of the microelectronic die 106 may be achieved by any known process, including but not limited to injection, transfer, and compression molding.
As shown in FIG. 5c, a plurality of conductive traces 224 are formed on an upper surface 226 of the flex component 202 and extend into vias 228 (formed through the flex component 202) to contact the contacts 208. The vias 228 may be formed by any known technique, but are general formed by laser ablation. The conductive traces 224 may also be formed by any known technique, such as photolithography.
A plurality of additional flex component layers are stacked by attaching one atop another, represented by elements 202' and 202", with additional conductive traces formed thereon, represented by elements 224' and 224", as shown in FIG. 5d. A layer of solder resist 232 is then applied over the uppermost flex component layer and conductive traces, represented by elements 202" and 224", respectively, as shown in FIG. 5e. A plurality of vias 234 are formed through the solder resist layer 232 to expose a portion of the uppermost conductive trace, represented as element 224", as shown in FIG. 5f. As shown in FIG. 5g, external contacts are formed on the conductive traces 224" (shown as solder balls 236), such as by any known plating technique.
Such COF packaging has been used in lower cost and/or lower volume (e.g., "low-end chips"). However, as COF packaging becomes a more common packaging technique, high-end chips are being packaged with the COF packaging technique. Unfortunately, one problem with COF packaging is that moisture can easily diffuse into the packages and cause metal corrosion and delamination of the flex component layers. As high-end chips are relatively expensive and, thus, must be reliable, such moisture related problems must be addressed.
Therefore, it would be advantageous to develop new apparatus and techniques to provide moisture barrier(s) for COF packaging, while utilizing commercially available, widely practiced microelectronic fabrication techniques.